The present invention relates to a semiconductor integrated circuit device for electrically erasing data in unit of a plurality of memory cells (blocks), more particularly to a flash EEPROM (Electrically Erasable Programmable Read-Only Memory) having a function of determining the presence of the overerased memory cells by monitoring the leek current from the column after the data erasing operation.
The memory cells constituting the flash EEPROM are each formed of a non-volatile transistor memory including a floating gate and a control gate forming a stack structure. In writing the data in the flash EEPROM, a write voltage is applied to the control gate and drain of the memory cell to generate hot electrons in a channel such that the hot electrons are injected into the floating gate.
While, in erasing the data written in the flash EEPROM, the source of the memory cell is applied with a high voltage to generate a high electric field between the source and the floating gate. With this high electric field, the electrons caught by the floating gate are discharged to the source by the tunnel effect, and the data stored in the flash EEPROM is erased.
In erasing the data written in the flash EEPROM, the overerasing, the phenomenon that the threshold voltage of the memory cell turned to have a negative polarity. The overerased memory cell (hereinafter referred to as "overerased cell") is constantly turned on even in the non-selected state. Accordingly, when the bit line to which the overerased cell is connected is connected to the memory cell which is turned off and stores "0" data, the "0" data cannot be read correctly even if the "0" data memory cell is selected.
In order to prevent the overerasing, the erasing method called as the intelligent erasing method wherein the erasing operation and the verifying operation are repeatedly performed to finish the erasing operation when the threshold voltage of the memory cell the data stored in which is erased latest is decreased lower than a predetermined voltage.
While, after the erasing operation, the threshold voltages of the memory cells in the flash EEPROM are distributed around a range wider than 2V, which is quite larger than 1V, the distribution range of the threshold voltages of the devices the data stored in which is erased with use of ultra violet ray. With such a large distribution range of the erasing threshold voltages, the lower limit of the reading voltage therein cannot be easily decreased. This is the bottleneck in decreasing the reading voltage. Further, the variation in the threshold voltages of the memory cells, which is generated in the manufacturing process, is thought to increase in future as a result of the reduction of the memory cell in size. In consideration of the above, the variation in the threshold voltages needs to be decreased.
In order to overcome the overerasing problem causing the variation in the threshold voltage, the process called as the compaction where it is checked whether of not any memory cell is overerased, and the threshold voltage of the overerased cell is turned to have a positive polarity needs to be performed. The compaction is performed by applying the write voltage to the drain of the overerased cell after erasing the data stored therein, to inject abalanche hot carriers into the overerased cell.
With this method, the threshold voltage of the overerased cell can be turned to have a positive polarity by applying the positive voltage to the overerased cell. It is no more than 100 ms enough to turn the threshold voltage of the overerased cell to have a positive polarity.
The above-mentioned compaction process is performed by simultaneously applying the control gates and the sources of the memory cells with a ground voltage (Vg=0V) and applying the drain with a positive voltage, and thus cannot be performed selectively for respective memory cells. Accordingly, the compaction process is usually performed simultaneously for a unit of memory cells connected to one or a plurality of columns (bit lines). In the compaction process, the overerased cell checking operation is performed by measuring the amount of the leak current from each columns in the state where all the word lines are grounded. The leak current amount of about 1.mu. to 5 .mu.A needs to be measured in this time, to find the overerased cell.
FIG. 1 schematically shows the conventional reading circuit in a flash EEPROM.
In this drawing, a plurality of memory cells MC in the same column are connected to a bit line BL at their drains. Each memory cell has a floating gate, a control gate, and source and drain. By injecting electrons into the floating gate, the threshold voltage of the memory cell is changed, thereby electrically writing (programming) data in the memory cell and electrically erasing data therefrom. In the writing operation, the data stores in the memory cells are electrically erased.
The bit line BL is connected, via a MOS transistor 91 for selecting a column, to a sense node N1 which is one of the sense nodes of a differential amplifier 92 for sensing data. The sense node N1 is connected to a load circuit 93 which is arranged between a power supply voltage V.sub.DD and the sense node N1.
A reference line RL is connected to a reference current source 94. The reference line RL is also connected, via a MOS transistor 95 arranged so as to correspond to the MOS transistor 91, to a sense node N2 which is the other one of the sense nodes of the differential amplifier 92. The sense node N2 is connected to a load circuit 96 which is arranged between a power supply voltage V.sub.DD and the sense node N2.
The memory cells MC is constituted such that only selected one of the control gates thereof is applied with a high level voltage in a read mode. The other memory cell are applied with a low level voltage. In a leak current check mode, all the memory cells are applied with the low level voltage.
Assume that the load circuit 96 as the load for the reference line is denoted as R1 and the load circuit 93 as a load for the bit line is denoted as R2, and the current flow from a reference current source 94 is denoted as I1, and the current flowing through the bit line BL is denoted as I2. Then, the potential (a sense potential) at the sense node N1 equals to the potential (a reference potential) at the sense node N2 when the relationship among them can be represented as R1.multidot.I1=R2.multidot.I2.
Accordingly, when the relationship is represented as I1&lt;(R2/R1).multidot.I2, it is determined that no leak current flows from the bit line BL. When the relationship is represented as I1&gt;(R2/R1).multidot.I2, it is determined that a leak current flows from the bit line BL.
According to the conventional device, the level of the current differs in a read mode and in a leak current check mode: when the current value in a read mode is set at 20 .mu.A and the that in a leak current check mode is set at 1 .mu.A, for example. In this time, the value of R1 is varied such that the relationship as R1 (in a read mode)&gt;R1 (in a leak current check mode) can be obtained. By setting the ratio of the above-represented values of R1 as 20, the amounts of the currents differentiated by 20 times can be determined.
However, in case of adopting a method in which the value of the resistance value R1 is set to be small one in a leak current check mode in the conventional data reading circuit, the signal amplitude in the bit line BL is extremely decreased, with the result that the reading margin is also decreased.
In the above case, the resistance value R1 is set small in a leak current check mode. In contrast, the resistance value R2 may be increased by 20 times to differentiate the resistance value. In this case, the signal amplitude in the bit line BL can be sufficiently maintained in a leak current check mode as in a read mode. However, a load element is constituted of a MOS transistor, in general. The MOS transistor having a large resistance value has a large area. The increase in area in this portion will increase in total area of the circuit, and the parasitic capacitance of the reference line connected to the sense node of the differential amplifier will be increased thereby. As a result, the alternate current characteristics in a read mode may be adversely affected.